Exemplary embodiments in accordance with principles of inventive concepts relate to a field effect transistor, and in particular, to a field effect transistor having a channel region to which strain is applied, and a method of fabricating the same.
A semiconductor device typically includes an integrated circuit of metal-oxide-semiconductor field effect transistors (MOSFETs). As device feature sizes diminish in order to continuously increase the capabilities of semiconductor devices, various obstacles to successful implementation, such as the short channel effect, for example, may be encountered. A method and apparatus for increasing MOSFET carrier mobility may provide the myriad benefits of increased device density/decreased feature size, lower power consumption, and improved device reliability.
One approach to increasing carrier mobility involves establishing a strain, through lattice constant mismatch, on a MOSFET's channel region. Source/Drain patterns may be formed with recessed portions of a substrate. The recessed portions of the substrate may then be filled with materials having a lattice constant different from that of the substrate, resulting in a strain on the channel region and increased carrier mobility. However, during a recessing step a device isolation layer may be exposed, resulting in difficulty growing material for the Source/Drain regions. In another approach, strain-relaxed buffer layers may be employed to exert a strain on a channel region, the process also employing a recessing step. However, with such an approach, the recessing step may relax the strain imposed on the channel region and, because the strain relaxed buffer layers may be exposed, subsequent formation of semiconductor material may be compromised.